1. Field of the Invention
The present invention relates to direct memory access (DMA) controllers for directly transferring data between memory and input/output (I/O) devices without using any central processing unit (CPU) in an information processor.
2. Description of the Prior Art
In general, it is a waste of time to output data to an I/O device from memory by means of a CPU. One of the fast ways to output data to an I/O device from memory is to directly output data to an I/O device from the data bus. Such DMA requires some hardware, which is called "DMA controller," for supplying addresses and control signals for transferring data to read or write in the memory or I/O device. Like the CPU, the DMA controller generates addresses to read or write in the memory and sends various control signals to the I/O device.
FIG. 3 shows a conventional DMA controller 17 for an information processor which includes an information processing unit 1 such as a CPU of an electronic computer; a random access memory (RAM) 2; a 4-channel address output device 3; four I/O devices 12; a bus access controller 11; and data, address, and control buses 4, 5, and 6 for interconnecting the CPU 1, the address output device 3 the RAM, and the I/O device 12. The RAM 2 is a dynamic RAM which requires periodic refreshing. Four channels are assigned to the I/O devices 12 corresponding to the channels 0-3 of the address output device 3. The DMA controller 17 includes a transfer counter 9 and a request signal generator 10. The request signal generator 10 is composed of flip-flops such as bistable multivibrators. The transfer counter 9 moves one count up every time the transfer of data of one byte, for example, is completed and generates a carry at 255 counts. This is represented by a DMA end signal e.
The operation will be described with reference to FIG. 4. First of all, one of the I/O devices generates a DMA request signal DRQ (No. 1) for data transfer with the RAM 2. This is a negative logic signal and is represented by DRQ. When the DMA request signal DRQ is applied to the request signal generator 10, the request signal generator 10 becomes H and stable there and outputs a bus request signal BRQ to the bus access controller 11. If there is neither DRAM refresh request r with high interrupt priority nor external HOLD request, the bus access controller 11 sends bus available signals BAK-A and BAK-B to the DMA controller 17 and the CPU 1, respectively. The CPU 1 then cuts off the data bus 4, the address bus 5, and the control bus 6 to stop the use of data from the RAM 2 The DMA controller 17, on the other hand, outputs to the address output device 3 an acknowledge signal DAK indicating that the buses 4-6 are available. The requesting I/O device 12 identified by the address output device 3 then enters a burst mode for a certain period in which 255 bytes of data are transferred directly to the RAM 2.
When a refresh request r is inputted during the DMA transfer, the DMA controller 17 stops while the address output device 3 releases the buses 4, 5, and 6 for refreshing and resumes DMA transfer when the memory refresh is completed When the transfer of 255 bytes of data is completed, the transfer counter 9 generates a DMA end signal e. This inverts the output BRQ of the request signal generator 10, and the bus access controller 11 cancels the bus available signal BAK-A. The DMA controller 17 then inhibits the acknowledge signal DAK so that the I/O device 12 is cut off from the buses 4, 5, and 6, which in turn are connected to the CPU 1.
If another I/O device 12 generates a similar request on the channel No. 0, the same operation as described above will be repeated Any request on the channel No. 0 during DMA transfer on the channel No. 1 is unacceptable and must wait until the transfer on the channel No. 1 is completed.
In the conventional DMA controller, however, the CPU 1 is unable to use the RAM 2 for a certain fixed period during the transfer of data in the burst mode. The CPU 1 performs an internal process during the DMA transfer and must wait for that time period even if it needs data from the RAM 2, resulting in the under utilization of the CPU 1.